ATX (Advanced Technology Extended) is a computer form factor designed by Intel in 1995. It was the first big change in computer case, motherboard, and power supply design in many years. ATX overtook AT completely as the default form factor for new systems. ATX addressed many of the AT form factor’s annoyances that had frustrated system builders. Other standards for smaller boards (including microATX, FlexATX and mini-ITX) usually keep the basic rear layout but reduce the size of the board and the number of expansion slot positions. In 2003, Intel announced the BTX standard, intended as a replacement for ATX. As of 2009, the ATX form factor remains a standard for do-it-yourselfers; BTX has however made inroads into pre-made systems.

The official specifications were released by Intel in 1995, and have been revised numerous times since, the most recent being version 2.3,^[1] released in 2007.

A full size ATX board is 12 in × 9.6 in (305 mm × 244 mm). This allows many ATX form factor chassis to accept microATX boards as well.

Types of random access memory

There are generally two broad categories of random access memory:

• DRAM memories (Dynamic Random Access Module), which are inexpensive. They are used essentially for the computer’s main memory
• SRAM memories (Static Random Access Module), which are fast and costly. SRAM memories are used in particular for the processor’s cache memory

Operation of the random access memory

The random access memory comprises hundreds of thousands of small capacitors that store loads. When loaded, the logical state of the capacitor is equal to 1, otherwise it is 0, meaning that each capacitor represents one memory bit.

Given that the capacitors become discharged they must be constantly recharged (the exact term isrefresh) at regular intervals, known as the refresh cycle. DRAM memories for example require refresh cycles of around 15 nanoseconds (ns).

Each capacitor is coupled with a transistor (MOS-type) enabling “recovery” or amendment of the status of the capacitor. These transistors are arranged in the form of a table (matrix) thus we access a memory box(also called memory point) via a line and a column.

Each memory point is thus characterised by an address which corresponds to a row number and a column number. This access is not instant and the access time period is known as latency time. Consequently, time required for access to data in the memory is equal to cycle time plus latency time.

Thus, for a DRAM memory, access time is 60 nanoseconds (35ns cycle time and 25ns latency time). On a computer, the cycle time corresponds to the opposite of the clock frequency; for example, for a computer with frequency of 200 MHz, cycle time is 5 ns (1/200*10⁶)).

Consequently a computer with high frequency using memories with access time much longer than the processor cycle time must perform wait states to access the memory. For a computer with frequency of 200 MHz using DRAM memories (and access time of 60ns), there are 11 wait states for a transfer cycle. The computer’s performance decreases as the number of wait states increases, therefore we recommend the use of faster memories.

RAM module formats

There are many type of random access memory. They exist in the form of memory modules that can be plugged into the mother board.

Early memories existed in the form of chips called DIP (Dual Inline Package). Nowadays, memories generally exist in the form of modules, which are cards that can be plugged into connectors for this purpose. There are generally three types of RAM module:

• modules in SIMM format (Single Inline Memory Module): these are printed circuit boards with one side equipped with memory chips. There are two types of SIMM modules, according to the number of connectors:
  • SIMM modules with 30 connectors (dimensions are 89x13mm) are 8-bit memories with which first-generation PCs were equipped (286, 386).

• • SIMM modules with 72 connectors (dimensions are 108x25mm) are memories able to store 32 bits of data simultaneously. These memories are found on PCs from the 386DX to the first Pentiums. On the latter, the processor works with a 64-bit data bus; this is why these computers must be equipped with two SIMM modules. 30-pin modules cannot be installed on 72-connector positions because a notch (at the centre of the connectors) would prevent it from being plugged in.

• modules in DIMM format (Dual Inline Memory Module) are 64-bit memories, which explains why they do not need pairing. DIMM modules have memory chips on both sides of the printed circuit board and also have 84 connectors on each side, giving them a total of 168 pins. In addition to having larger dimensions than SIMM modules (130x25mm), these modules have a second notch to avoid confusion.

It may be interesting to note that the DIMM connectors have been enhanced to make insertion easier, thanks to levers located either side of the connector.

Smaller modules also exist; they are known as SO DIMM (Small Outline DIMM), designed for portable computers. SO DIMM modules have only 144 pins for 64-bit memories and 77 pins for 32-bit memories.

• modules in RIMM format (Rambus Inline Memory Module, also called RD-RAM or DRD-RAM) are 64-bit memories developed by Rambus. They have 184 pins. These modules have two locating notches to avoid risk of confusion with the previous modules.

Given their high transfer speed, RIMM modules have a thermal film which is supposed to improve heat transfer.

As for DIMMs, smaller modules also exist; they are known as SO RIMM (Small Outline RIMM), designed for portable computers. SO RIMM modules have only 160 pins.�

DRAM PM

The DRAM (Dynamic RAM) is the most common type of memory at the start of this millennium. This is a memory whose transistors are arranged in a matrix in rows and columns. A transistor, coupled with a capacitor, gives information on a bit. Since 1 octet contains 8 bits, a DRAM memory module of 256 Mo will thus contain 256 * 2^10 * 2^10 = 256 * 1024 * 1024 = 268,435,456 octets = 268,435,456 * 8 = 2,147,483,648 bits = 2,147,483,648 transistors. A module of 256 Mo thus has a capacity of 268,435,456 octets, or 268 Mo! These memories have access times of 60 ns.

Furthermore, access to memory generally concerns data stored consecutively in the memory. Thus burst mode allows access to the three pieces of data following the first piece with no additional latency time. In this burst mode, time required to access the first piece of data is equal to cycle time plus latency time, and the time required to access the other three pieces of data is equal to just the cycle time; the four access times are thus written in the form X-Y-Y-Y, for example 5-3-3-3 indicates a memory for which 5 clock cycles are needed to access the first piece of data and 3 for the subsequent ones.

DRAM FPM

To speed up access to the DRAM, there is a technique, known as paging, which involves accessing data located in the same column by changing only the address of the row, thus avoiding repetition of the column number between reading of each row. This is known as DRAM FPM (Fast Page Mode). FPM achieves access times of around 70 to 80 nanoseconds for operating frequency between 25 and 33 Mhz.

DRAM EDO

DRAM EDO (Extended Data Out, sometimes also called hyper-page“) was introduced in 1995. The technique used with this type of memory involves addressing the next column while reading the data in a column. This creates an overlap of access thus saving time on each cycle. EDO memory access time is thus around 50 to 60 nanoseconds for operating frequency between 33 and 66 Mhz.

Thus the RAM EDO, when used in burst mode, achieves 5-2-2-2 cycles, representing a gain of 4 cycles on access to 4 pieces of data. Since the EDO memory did not work with frequencies higher than 66 Mhz, it was abandoned in favour of the SDRAM.

SDRAM

The SDRAM (Synchronous DRAM), introduced in 1997, allows synchronised reading of data with the mother-board bus, unlike the EDO and FPM memories (known as asynchronous) which have their own clock. The SDRAM thus eliminates waiting times due to synchronisation with the mother-board. This achieves a 5-1-1-1 burst mode cycle, with a gain of 3 cycles in comparison with the RAM EDO. The SDRAM is thus able to operate with frequency up to 150 Mhz, allowing it to achieve access times of around 10 ns.

DR-SDRAM (Rambus DRAM)

The DR-SDRAM (Direct Rambus DRAM) is a type of memory that lets you transfer data to a 16-bit bus at frequency of 800Mhz, giving it a bandwidth of 1.6 Go/s. As with the SDRAM, this type of memory is synchronised with the bus clock to enhance data exchange. However, the RAMBUS memory is a proprietary technology, meaning that any company wishing to produce RAM modules using this technology must pay royalties to both RAMBUS and Intel.

DDR-SDRAM

The DDR-SDRAM (Double Data Rate SDRAM) is a memory, based on the SDRAM technology, which doubles the transfer rate of the SDRAM using the same frequency.

Data are read or written into memory based on a clock. Standard DRAM memories use a method known as SDR (Single Data Rate) involving reading or writing a piece of data at each leading edge.

The DDR doubles the frequency of reading/writing, with a clock at the same frequency, by sending data to each leading edge and to each trailing edge.

DDR memories generally have a product name such as PCXXXX where “XXXX” represents the speed in Mo/s.

DDR2-SDRAM

DDR2 (or DDR-II) memory achieves speeds that are twice as high as those of the DDR with the same external frequency.

QDR (Quadruple Data Rate or quad-pumped) designates the reading and writing method used. DDR2 memory in fact uses two separate channels for reading and writing, so that it is able to send or receive twice as much data as the DDR.

DDR2 also has more connectors than the classic DDR (240 for DDR2 compared with 184 for DDR).

summary table

The table below gives the equivalence between the mother-board frequency (FSB), the memory (RAM) frequency and its speed:

Memory	Name	Frequency (RAM)	Frequency (FSB)	Speed
DDR200	PC1600	200 MHz	100 MHz	1.6 Go/s
DDR266	PC2100	266 MHz	133 MHz	2.1 Go/s
DDR333	PC2700	333 MHz	166 MHz	2.7 Go/s
DDR400	PC3200	400 MHz	200 MHz	3.2 Go/s
DDR433	PC3500	433 MHz	217 MHz	3.5 Go/s
DDR466	PC3700	466 MHz	233 MHz	3.7 Go/s
DDR500	PC4000	500 MHz	250 MHz	4 Go/s
DDR533	PC4200	533 MHz	266 MHz	4.2 Go/s
DDR538	PC4300	538 MHz	269 MHz	4.3 Go/s
DDR550	PC4400	550 MHz	275 MHz	4.4 Go/s
DDR2-400	PC2-3200	400 MHz	100 MHz	3.2 Go/s
DDR2-533	PC2-4300	533 MHz	133 MHz	4.3 Go/s
DDR2-667	PC2-5300	667 MHz	167 MHz	5.3 Go/s
DDR2-675	PC2-5400	675 MHz	172.5 MHz	5.4 Go/s
DDR2-800	PC2-6400	800 MHz	200 MHz	6.4 Go/s

People in the computer industry commonly use the term “memory” to refer to RAM (Random Access Memory). As your processor cranks on your game, it uses RAM to store some of the data needed to make your game work. While all forms of memory work together, RAM is considered the main memory since most data, regardless of its source, is stored in RAM before it is registered in any other storage device. Consequently, RAM is used millions of times every second. A computer uses Ram to hold temporary instructions and data needed to complete tasks. This enables the computer’s CPU (Central Processing Unit), to access instructions and data stored in memory very quickly.

Computer memory is extremely important to computer operation. Files and programs are loaded  into memory from external media like fixed disks (hard drives) and removable disks (floppies tapes). Memory can be built right into a system board, but it is more typically attached to the system board in the form of a chip or module. Inside these chips are microscopic digital switches which are used to represent binary data.

A good example of this is when the CPU loads an application program – such as a word processing or page layout program – into memory, thereby allowing the application program to work as quickly and efficiently as possible. In practical terms, having the program loaded into memory means that you can get work done more quickly with less time spent waiting for the computer to perform tasks.

The process begins when you enter a command from your keyboard. The CPU interprets the command and instructs the hard drive to load the command or program into memory. Once the data is loaded into memory, the CPU is able to access it much more quickly than if it had to retrieve it from the hard drive.

This process of putting things the CPU needs in a place where it can get at them more quickly is similar to placing various electronic files and documents you’re using on the computer into a single file folder or directory. By doing so, you keep all the files you need handy and avoid searching in several places every time you need them.

In general the more RAM a computer has the faster the computer operates. Why? RAM is where all the information is kept just before the computer needs to use it.

Think of it this way. During a conversation a person can speak without interruption if everything being talked about is in his or her memory. However, if a person does not have enough memory and has to look something up during the course of the conversation, in a book or newspaper, then the conversation stops until the needed information is found.

Computers are very similar; they can continue processing without interruption as long as all needed information is in memory (RAM). When that is not the case, the computer stops, retrieves the needed information from storage (i.e. Hard drive, CD, disk) and places it into memory and then continues processing. The more interruptions the computer receives to retrieve information the slower the computer. The more memory a computer has, the fewer interruptions and the faster the computer operates. More memory equates to more speed.

These days, no matter how much memory your computer has, it never seems to be quite enough. Not long ago, it was unheard of for a PC (Personal Computer), to have more than 1 or 2 MB (Megabytes) of memory. Today, most systems require 64MB to run basic applications. And up to 256MB or more is needed for optimal performance when using graphical and multimedia programs.

As an indication of how much things have changed over the past two decades, consider this: in 1981, referring to computer memory, Bill Gates said, “640K (roughly 1/2 of a megabyte) ought to be enough for anybody.”

 

DDR

Double Data Rate synchronous dynamic random access memory (or also known as DDR SDRAM) is a class of memory integrated circuits used in computers.

Compared to the preceding single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy.^[1] [2]

The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to lower the clock frequency. One advantage of keeping the clock frequency down is that it reduces thesignal integrity requirements on the circuit board connecting the memory to the controller. The name “double data rate” refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice thebandwidth of a single data rate (SDR) SDRAM running at the same clock frequency, due to this double pumping.

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) x 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

“Beginning in 1996 and concluding in June 2000, JEDEC developed the DDR (Double Data Rate) SDRAM specification (JESD79).”^[3] JEDEC has set standards for data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules. As DDR SDRAM is superseded by the newer DDR2 SDRAM, the older DDR version is sometimes referred to as DDR1 SDRAM.

DDR2

DDR2 SDRAM is a double data rate synchronous dynamic random access memory interface. It supersedes the original DDR SDRAM specification and the two are not compatible. In addition to double pumping the data bus as in DDR SDRAM (transferring data on the rising and falling edges of the bus clock signal), DDR2 allows higher bus speed and requires lower power by running the internal clock at one quarter the speed of the data bus. The two factors combine to require a total of 4 data transfers per internal clock cycle.

With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate) × 2 (for bus clock multiplier) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200 MB/s.

Since the DDR2 clock runs at half the DDR clock rate, DDR2 memory operating at the same external data bus clock rate as DDR will provide the same bandwidth but with higher latency, resulting in inferior performance. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules.

DDR3

In electronic engineering, DDR3 SDRAM or double-data-rate three synchronous dynamic random access memory is a random access memory interface technology used for high bandwidth storage of the working data of a computer or other digital electronic devices. DDR3 is part of the SDRAM family of technologies and is one of the many DRAM (dynamic random access memory) implementations.

DDR3 SDRAM is an improvement over its predecessor, DDR2 SDRAM, and the two are not compatible. The primary benefit of DDR3 is the ability to transfer at twice the data rate of DDR2 (I/O at 8× the data rate of the memory cells it contains), thus enabling higher bus rates and higher peak rates than earlier memory technologies. In addition, the DDR3 standard allows for chip capacities of 512 megabits to 8 gigabits, effectively enabling a maximum memory module size of 16 gigabytes.

With data being transferred 64 bits at a time per memory modu

JEDEC standard modules

Standard name	Memory clock	Cycle time	I/O bus clock	Data rate	Module name	Peak transfer rate	Timings
DDR3-800	100 MHz	10 ns	400 MHz	800 MT/s	PC3-6400	6400 MB/s	5-5-5 6-6-6
DDR3-1066	133 MHz	7.5 ns	533 MHz	1066 MT/s	PC3-8500	8533 MB/s	6-6-6 7-7-7 8-8-8
DDR3-1333	166 MHz	6 ns	667 MHz	1333 MT/s	PC3-10600	10667 MB/s	7-7-7 8-8-8 9-9-9 10-10-10
DDR3-1600	200 MHz	5 ns	800 MHz	1600 MT/s	PC3-12800	12800 MB/s	8-8-8 9-9-9 10-10-10 11-11-11

Bits And Bytes Conversion Tables

In computer systems a byte is a binary unit of measurement used to refer to disk storage space in a hard disk drive or Random Access Memory (RAM) memory on computer systems.

It takes 8 Bits to create one Byte where a Bit is also a binary digit consisting of a value of 0 or 1. For example 10101010, 00000000, 11111111 are all 8 bits long and form 1 Byte. Put simply a Byte is a collection of Bits.

The chart directly below will provide you with the conversions and the second chart shows you to abbreviations for each.

Unit	Equals
1 Bit	Binary Digit
8 Bits	1 Byte
1024 Bytes	1 Kilobyte
1024 Kilobytes	1 Megabyte
1024 Megabytes	1 Gigabyte
1024 Gigabytes	1 Terabyte
1024 Terabytes	1 Petabyte
1024 Petabytes	1 Exabyte -
1024 Exabytes	1 Zettabyte
1024 Zettabytes	1 Yottabyte
1024 Yottabytes	1 Brontobyte

 

Abbreviations

Unit	Abbreviation
Bit	b
Byte	B
Kilo Byte	KB
Mega Byte	MB
Giga Byte	GB
Tera Byte	TB
Peta Byte	PB
Exa Byte	EB
Zetta Byte	ZB
Yotta Byte	YB
Bronto Byte	BB

PCI

Conventional PCI (part of the PCI Local Bus standard and often shortened to PCI) is a computer bus for attaching hardware devices in a computer. These devices can take either the form of an integrated circuitfitted onto the motherboard itself, called a planar device in the PCI specification, or an expansion card that fits into a slot. The name PCI is an initialism formed from Peripheral Component Interconnect. The PCI Local Bus is common in modern PCs, where it has displaced ISA and VESA Local Bus as the standard expansion bus, and it also appears in many other computer types. Despite the availability of faster interfaces such as PCI-X and PCI Express, conventional PCI remains a very common interface.

PCI EXPRESS HISTORY

While in development, PCIe was initially referred to as HSI (for High Speed Interconnect), and underwent a name change to 3GIO (for 3rd Generation I/O) before finally settling on its PCI-SIG name PCI Express. It was first drawn up by a technical working group named the Arapaho Work Group (AWG) which for initial drafts consisted of an Intel only team of architects. Subsequently the AWG was expanded to include industry partners.

PCIe is a technology under constant development and improvement. The current PCI Express implementation is version 2.1, with version 3.0 already proposed. The following subsections briefly describe PCIe versions 1.0 through 3.0.

[edit]PCI Express 1.0

In 2004, Intel introduced PCIe 1.0, with a data rate of 250 MB/s and a transfer rate of 2.5 GT/s.

[edit]PCI Express 2.0

PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.^[9] The PCIe 2.0 standard doubles the per-lane throughput from the PCIe 1.0 standard’s 250 MB/s to 500 MB/s. This means a 32-lane PCI connector (x32) can support throughput up to 16 GB/s aggregate. The PCIe 2.0 standard uses a base clock speed of 5.0 GHz, while the first version operates at 2.5 GHz.

PCIe 2.0 motherboard slots are fully backward compatible with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v 2.0 will be able to work with the other being v 1.1 or v 1.0.

The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.^[10]

In June 2007 Intel released the specification of the Intel P35 chipset which supports only PCIe 1.1, not PCIe 2.0.^[11] Some people may be confused by the P35 block diagram which states the Intel P35 has a PCIe x16 graphics link (8 GB/s) and 6 PCIe x1 links (500 MB/s each).^[12] For simple verification one can view the P965 block diagram which shows the same number of lanes and bandwidth but was released before PCIe 2.0 was finalized.^{[original research?]} Intel’s first PCIe 2.0 capable chipset was theX38 and boards began to ship from various vendors (Abit, Asus, Gigabyte) as of October 21, 2007.^[13] AMD started supporting PCIe 2.0 with its RD700 chipset series and nVidia started with the MCP72.^[14] The specification of the Intel P45 chipset includes PCIe 2.0.

[edit]PCI Express 2.1

PCI Express 2.1 supports a large proportion of the management, support, and troubleshooting systems planned to be fully implemented in PCI Express 3.0. But, the speed is the same as PCI Express 2.0.

[edit]PCI Express 3.0

In August 2007, PCI-SIG announced that PCI Express 3.0 will carry a bit rate of 8 gigatransfers per second. The final specification is due in the second quarter of 2010 and will be backwards compatible with existing PCIe implementations.^[15] New features for PCIe 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.^[16]

Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, PCI-SIG’s analysis found out that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCIe protocol stack.

PCIe 2.0 delivers 5 GT/s but employed an 8b/10b encoding scheme which took 20 percent overhead on the overall raw bit rate. By removing the requirement for the 8b/10b encoding scheme, and replacing it with a 128b/130b encoding scheme with only ~1.5 percent overhead,^[17] PCIe 3.0′s 8 GT/s bit rate effectively delivers double PCIe 2.0 bandwidth. According to an official press release by PCI-SIG on 8 August 2007:

“The final PCIe 3.0 specifications, including form factor specification updates, may be available by late 2009, and could be seen in products starting in 2010 and beyond.”^[18]

As of January 2010, the release of the final specifications has been delayed until Q2 2010.^[19] PCI-SIG expects the PCIe 3.0 specifications to undergo rigorous technical vetting and validation before being released to the industry. This process, which was followed in the development of prior generations of the PCIe Base and various form factor specifications, includes the corroboration of the final electrical parameters with data derived from test silicon and other simulations conducted by multiple members of the PCI-SIG.

[edit]Current status

PCI Express has replaced AGP as the default interface for graphics cards on new systems. With a few exceptions, all graphics cards being released as of 2009 from ATI and NVIDIA use PCI Express. NVIDIA uses the high bandwidth data transfer of PCIe for its Scalable Link Interface (SLI) technology, which allows multiple graphics cards of the same chipset and model number to be run in tandem, allowing increased performance. ATI also has developed a multi-GPU system based on PCIe called CrossFire. AMD and NVIDIA have released motherboard chipsets which support up to four PCIe ×16 slots, allowing tri-GPU and quad-GPU card configurations.

Uptake for other forms of PC expansion has been much slower and conventional PCI remains dominant. PCI Express is commonly used for disk array controllers, onboard gigabit Ethernet and wi-fi but add-in cards are still generally conventional PCI, particularly at the lower end of the market. Sound cards, modems, serial port cards and other cards with low-speed interfaces are still nearly all conventional PCI. For this reason most motherboards supporting PCI Express offer conventional PCI slots as well.

ExpressCard has been introduced on several mid- to high-range laptops such as Apple’s MacBook Pro line. Unlike desktops, however, laptops frequently only have one expansion slot. Replacing the PC card slot with ExpressCard slot means a loss in compatibility with PC-card devices.

he initial rollout of PCI-Express provides three consumer flavors: x1, x2, and x16. The number represents the number of lanes: x1 has 1 lane; x2 has 2 lanes, and so on. Each lane is bi-directional and consists of 4 pins. Lanes have a delivery transfer rate of 250 MB/ps in each direction for a total of 500 MB/ps, per lane.

PCIe	Lanes	Pins	MB/ps	Purpose
x1	1	4	500 MB/ps	Device
x2	2	8	1000 MB/ps = 1 GB/ps	Device
x16	16	64	8000 MB/ps = 8 GB/ps	Graphics Card

 

 

 Transfer Transfer
IDE Rate Rate Pins
Drive PIO MBytes DMA MBytes in
Type Mode per sec Mode per sec Cable
ATA       0      3.3     0      4.2      40
ATA       1      5.2                     40
ATA       2      8.3
ATA-2, 3  3     11.1     1     13.3      40
ATA-2, 3  4     16.6     2     16.6      40
ATA-4 (ATA-33)           2     33.3      40
ATA-5                    0     16.6      40
ATA-5                    1     25.0      40
ATA-5 (ATA-33)           2     33.3      40
ATA-5                    3     44.4      80
ATA-5 (ATA-66)           4     66.6      80
ATA-6 (ATA-100)          5    100.0      80
ATA-7 (ATA-133)          5    133.0      80
Serial ATA (SATA)        5    150.0       4
Serial ATA II (SATA II)  5    300.0       4

Internal IDE Cables

Starting with ATA-66 drives, 80-wire cables (with 40 more ground wires) replaced the 40-wire ribbon cable. They plug into the same 40-pin socket with one pin removed.

ATA

Short for Advanced Technology Attachment, a disk drive implementation that integrates the controller on the disk drive itself. There are several versions of ATA, all developed by the Small Form Factor (SFF) Committee:

•  ATA: Known also as IDE, supports one or two hard drives, a 16-bit interface and PIO modes 0, 1 and 2.
• ATA-2: Supports faster PIO modes (3 and 4) and multiword DMA modes (1 and 2). Also supports logical block addressing (LBA) and block transfers. ATA-2 is marketed as Fast ATA and Enhanced IDE (EIDE).
• ATA-3: Minor revision to ATA-2.
• Ultra-ATA: Also called Ultra-DMA, ATA-33, and DMA-33, supports multiword DMA mode 3 running at 33 MBps.
• ATA/66: A version of ATA proposed by Quantum Corporation, and supported by Intel, that doubles ATA’s throughput to 66 MBps.
• ATA/100: An updated version of ATA/66 that increases data transfer rates to 100 MBps.

ATA also is called Parallel ATA. Contrast with Serial ATA.

Yahoo! Messenger Archive Location

Update: This tip also applies if you want to find Yahoo! Messenger’s archive location in Windows 7.

Backing up Yahoo! Messenger’s message archive is a task I do every so often. Since I switched to Vista, I’ve been unable to figure out where the log files have gone. Surely, It’s no longer under Y!M’s installation directory.

In Windows XP, the location of the log files (.dat) is typically as follows, unless the installation directory was changed:

C:\Program Files\Yahoo!\Messenger\Profiles\<yahoo_username>

In Windows Vista, the new location of the log files have been moved to the user’s AppData directory:

C:\Users\<windows_usrnme>\AppData\Local\VirtualStore\Program Files\Yahoo!\Messenger\Profiles\<yahoo_username>

C:\Users\<windows_usrnme>\AppData\Local\VirtualStore\Program Files (x86)\Yahoo!\Messenger\Profiles\<yahoo_username> (for x86 version of Windows)

Accessing this folder is another story, however. From my experience, navigating to the directory crashes Windows Explorer. To access the directory, just copy and paste the Profiles folder path shown above into Windows Explorer’s address bar. Change <windows_usrnme> and <yahoo_username> as necessary.

Cat5e and Cat6 Comparision

Category 6 Cabling System and Application

Why do I need all the bandwidth of category 6? As far as I know, there is no application today that requires 200 MHz of bandwidth.

Bandwidth precedes data rates just as highways come before traffic. Doubling the bandwidth is like adding twice the number of lanes on a highway. The trends of the past and the predictions for the future indicate that data rates have been doubling every 18 months. Current applications running at 1 Gb/s are really pushing the limits of category 5e cabling. As streaming media applications such as video and multi-media become commonplace, the demands for faster data rates will increase and spawn new applications that will benefit from the higher bandwidth offered by category 6. This is exactly what happened in the early 90’s when the higher bandwidth of category 5 cabling compared to category 3 caused most LAN applications to choose the better media to allow simpler, cost effective, higher speed LAN applications, such as 100BASE-TX. Note: Bandwidth is defined as the highest frequency up to which positive power sum ACR (Attenuation to Crosstalk Ratio) is greater than zero.

What is the general difference between category 5e and category 6?

The general difference between category 5e and category 6 is in the transmission performance, and extension of the available bandwidth from 100 MHz for category 5e to 200 MHz for category 6. This includes better insertion loss, near end crosstalk (NEXT), return loss, and equal level far end crosstalk (ELFEXT). These improvements provide a higher signal-to-noise ratio, allowing higher reliability for current applications and higher data rates for future applications.

Will category 6 supersede category 5e?

Yes, analyst predictions and independent polls indicate that 80 to 90 percent of all new installations will be cabled with category 6. The fact that category 6 link and channel requirements are backward compatible to category 5e makes it very easy for customers to choose category 6 and supersede category 5e in their networks. Applications that worked over category 5e will work over category 6.

What does category 6 do for my current network vs. category 5e?

Because of its improved transmission performance and superior immunity from external noise, systems operating over category 6 cabling will have fewer errors vs. category 5e for current applications. This means fewer re-transmissions of lost or corrupted data packets under certain conditions, which translates into higher reliability for category 6 networks compared to category 5e networks.

When should I recommend or install category 6 vs. category 5e?

From a future proofing perspective, it is always better to install the best cabling available. This is because it is so difficult to replace cabling inside walls, in ducts under floors and other difficult places to access. The rationale is that cabling will last at least 10 years and will support at least four to five generations of equipment during that time. If future equipment running at much higher data rates requires better cabling, it will be very expensive to pull out category 5e cabling at a later time to install category 6 cabling. So why not do it for a premium of about 20 percent over category 5e on an installed basis?

What is the shortest link that the standard will allow?

There is no short length limit. The standard is intended to work for all lengths up to 100 meters. There is a guideline in ANSI/TIA/EIA-568-B.1 that says the consolidation point should be located at least 15 meters away from the telecommunications room to reduce the effect of connectors in close proximity. This recommendation is based upon worst-case performance calculations for short links with four mated connections in the channel.

What is a “tuned” system between cable and hardware? Is this really needed if product meets the standard?

The word “tuned” has been used by several manufacturers to describe products that deliver headroom to the category 6 standard. This is outside the scope of the category 6 standard. The component requirements of the standard have been carefully designed and analyzed to assure channel compliance and electrical/ mechanical interoperability.

What is impedance matching between cable and hardware? Is this really needed if product meets the standard?

The standard has no impedance matching requirements. These are addressed by having return loss requirements for cables, connectors, and patch cords.

Is there a use for category 6 in the residential market?

Yes, category 6 will be very effective in the residential market to support higher Internet access speeds while facilitating the more stringent Class B EMC requirements (see also the entire FCC Rules and Regulations, Title 47, Part 15). The better balance of category 6 will make it easier to meet the residential EMC requirements compared to category 5e cabling. Also, the growth of streaming media applications to the home will increase the need for higher data rates which are supported more easily and efficiently by category 6 cabling.

Why wouldn’t I skip category 6 and go straight to optical fiber?

You can certainly do that but will find that a fiber system is still very expensive. Ultimately, economics drive customer decisions, and today optical fiber together with optical transceivers is about twice as expensive as an equivalent system built using category 6 and associated copper electronics. Installation of copper cabling is more craft-friendly and can be accomplished with simple tools and techniques. Additionally, copper cabling supports the emerging Data Terminal Equipment (DTE) power standard under development by IEEE (802.3af).

What is meant by the term “Electrically Balanced”?

A simple open wire circuit consisting of two wires is considered to be a uniform, balanced transmission line. A uniform transmission line is one which has substantially identical electrical properties throughout its length, while a balanced transmission line is one whose two conductors are electrically alike and symmetrical with respect to ground and other nearby conductors.* “Electrically balanced” relates to the physical geometry and the dielectric properties of a twisted pair of conductors. If two insulated conductors are physically identical to one another in diameter, concentricity, dielectric material and are uniformly twisted with equal length of conductor, then the pair is electrically balanced with respect to its surroundings. The degree of electrical balance depends on the design and manufacturing process. Category 6 cable requires a greater degree of precision in the manufacturing process. Likewise, a category 6 connector requires a more balanced circuit design. For balanced transmission, an equal voltage of opposite polarity is applied on each conductor of a pair. The electromagnetic fields created by one conductor cancel out the electromagnetic fields created by its “balanced” companion conductor, leading to very little radiation from the balanced twisted pair transmission line. The same concept applies to external noise that is induced on each conductor of a twisted pair. A noise signal from an external source, such as radiation from a radio transmitter antenna generates an equal voltage of the same polarity, or “common mode voltage,” on each conductor of a pair. The difference in voltage between conductors of a pair from this radiated signal, the “differential voltage,” is effectively zero. Since the desired signal on the pair is the differential signal, the interference does not affect balanced transmission. The degree of electrical balance is determined by measuring the “differential voltage” and comparing it to the “common mode voltage” expressed in decibels (dB). This measurement is called Longitudinal Conversion Loss “LCL” in the Category 6 standard. * The ABC’s of the telephone Vol. 7

Category 6 Cable Questions
What is the difference between enhanced category 5e cable rated for 400 MHz and category 6 cable rated for 250 MHz?

Category 5e requirements are specified up to 100 MHz. Cables can be tested up to any frequency that is supported by the test equipment, but such measurements are meaningless without the context of applications and cabling standards. The category 6 standard sets minimum requirements up to 250 MHz for cables, connecting hardware, patch cords, channels and permanent links, and therefore guarantees reasonable performance that can be utilized by applications.

Why did all category 6 cable used to have a spline, and now is offered without one?

Some category 6 cable designs have a spline to increase the separation between pairs and also to maintain the pair geometry. This additional separation improves NEXT performance and allows category 6 compliance to be achieved. With advances in technology, manufacturers have found other ways of meeting category 6 requirements. The bottom line is the internal construction of the cable does not matter, so long as it meets all the transmission and physical requirements of category 6. The standard does not dictate any particular method of cable construction.

Is there a limitation on the size of bundles one can have with category 6? Can you have 200-300 and still pass category 6?

There is no limit imposed by the standards on the maximum number of category 6 cables in a bundle. This is a matter for the market and the industry to determine based on practical considerations. It should be pointed out that after six or eight cables, the performance in any cable will not change significantly since the cables will be too far away to add any additional external (or alien) NEXT.

Category 6 Patch Cord Questions
Will contractors be able to make their own patch cords?

Category 6 patch cords are precision products, just like the cables and the connectors. They are best manufactured and tested in a controlled environment to ensure consistent, reliable performance. This will ensure interoperability and backward compatibility. All this supports patch cords as a factory-assembled product rather than a field-assembled product.

Do you have to use the manufacturer’s patch cords to get category 6 performance?

The category 6 standard has specifications for patch cords and connectors that are intended to assure interoperable category 6 performance. If manufacturers can demonstrate that each component meets the requirements in the standard, minimum category 6 performance will be achieved. However, manufacturers may also design their products to perform better than the minimum category 6 requirements, and in these cases compatible patch cords and connectors may lead to performance above the minimum category 6 requirements.

Category 6 Testing Questions Why do field tester manufacturers offer many different link adapters if everyone meets the standard?

This was an interim solution while the standard was still being developed and the interoperability requirements were not yet established. It is likely that soon one or more adapters will work for testing of cabling from all vendors.

Would you get passing test results if you used a link adapter not recommended by a manufacturer?

You should expect to get passing results if both the link adapter interface and the mating jack that is part of the link are both compliant to category 6 requirements.

Category 6 Connecting Hardware Questions
Are the connectors for category 5e and category 6 different? Why are they more expensive?

Although category 6 and category 5e connectors may look alike, category 6 connectors have much better transmission performance. For example, at 100 MHz, NEXT of a category 5e connector is 43 decibels (dB), while NEXT of a category 6 connector is 54 dB. This means that a cat6 connector couples about 1/12 of the power that a cat5e connector couples from one pair to another pair. Conversely, one can say that a category 6 connector is 12 times less “noisy” compared to a category 5e connector. This vast improvement in performance was achieved with new technology, new processes, better materials and significant R&D resources, leading to higher costs for manufacturers.

What will happen if I mix and match different manufacturers’ hardware together?

If the components are category 6 compliant, then you will be assured of category 6 performance.